Semiconductor technology has shown a general trend towards dramatic increases in integrated circuit speed and density. Both of these trends are fueled by a general reduction in device (active element) geometries. As semiconductor devices become smaller, the distances between them on a semiconductor die become smaller, and parasitics (such as parasitic capacitances) and switching currents become smaller. In technologies such as CMOS, where overall current draw and switching speed characteristics are dominated by the effects of parasitics, the result is a reduction in total power consumption at the same time as switching speed is improved. Overall speed is further improved by the reduction in signal propagation time between active devices (e.g., transistors) resulting from the shorter distances involved. In today's high speed integrated circuitry based on sub-micron geometries, delays in the tens or hundreds of picoseconds can be appreciable.
Typically, integrated circuit dies (chips, or semiconductor dies) are diced (cut apart, or singulated) from a semiconductor wafer and are assembled into integrated circuit packages which have pins, leads, solder (ball) bumps, or conductive pads by which electrical connections may be made from external systems to the integrated circuit chip. These packages are then typically applied to circuit board assemblies comprising systems of interconnected integrated circuit chips.
The aforementioned dramatic improvements in integrated circuit speed and density have placed new demands on integrated circuit assemblies, both at the chip and circuit board levels. Without attendant improvements in these areas, much of the benefit of high device speed is lost. Wiring propagation delays and transmission line effects, in integrated circuit packages and on circuit board assemblies, which were once negligible are now significant factors in the overall performance of systems based on high-speed integrated circuitry. In order to achieve the potential higher system-level performance opportunities afforded by the new high-density technologies, it is necessary to reduce the amount of signal propagation time between integrated circuits.
Another significant factor in achieving high system-level performance is signal drive capability. Longer signal paths are susceptible to noise (cross-talk, etc.) and require low-impedance, high-current drive circuits on the integrated circuit chips (dies). Such circuits tend to occupy large portions of the die area (either reducing the area available for other circuitry or increasing the overall die size), and can introduce significant delays of their own. Clearly, shorter signal paths and their attendant low signal drive current requirements are desirable to achieve high performance.
In the prior art, a number of high density chip assemblies and packages have been proposed and implemented. One such technique is commonly known as "chip-on-board" technology, whereby integrated circuit dies are bonded directly to die mounting areas on a circuit board substrate (e.g., ceramic, fiberglass, etc.) and are wire bonded (with thin "bond wires") to traces on the circuit board in areas adjacent to the edges of the dies. The elimination of the traditional integrated circuit package permits chips to be placed much closer together than would otherwise be possible, thereby shortening signal paths and reducing delays.
Examples of prior-art "chip-on-board" technology may be found in Japanese Patent No. 60-250639, issued Dec. 11, 1985 to Kazunori Narita, and in Japanese Patent No. 53-39068, issued Oct. 4, 1978 to Yoshiharu Nagayama.
Another high-density, high-performance packaging technique in the prior art makes use of "flip chips", whereby solder bumps (or conductive polymer bumps, or the like) are provided on the top surfaces of integrated circuit dies which are then "flipped" and mounted to a substrate which has patterns of contact pads arranged in register with the solder bumps. The substrate is usually a printed circuit board, "silicon circuit board" ceramic substrate, or other suitable planar substrate with a conductive wiring pattern on it. The substrate is laid out to accommodate one or more such "flip chips", making high-density interconnection of integrated circuit chips possible. This technique permits even closer spacing of integrated circuit dies than the aforementioned chip-on-board technique, because connections are made under the dies, saving the space which would otherwise be occupied by bond wires.
Examples of various prior-art "flip-chip" constructions are found in U.S. Pat. No. 3,388,301, issued Jun. 11, 1968 to B. D. James; U.S. Pat. No. 4,545,610, issued Oct. 8, 1985 to Lakritz et al.; U.S. Pat. No. 4,190,855, issued Feb. 26, 1980 to Inoue; U.S. Pat. No. 4,811,082, issued Mar. 7, 1989 to Jacobs et al.; U.S. Pat. No. 4,926,241, issued May 15, 1990 to Carey; U.S. Pat. No. 5,039,628, issued Aug. 13, 1991 to Carey; U.S. Pat. No. 4,970,575, issued Nov. 13, 1990 to Soga et al.; U.S. Pat. No. 3,871,014, issued Mar. 11, 1975 to King et al.; Japanese Patent No. 61-142750, issued Jun. 30, 1986 to Toru Kawanobe; Japanese Patent No. 61-145838, issued Jul. 3, 1986 to Kishio Yokouchi; Japanese Patent No. 57-210638, issued Dec. 24, 1982 to Toshio Hida; and in "Wafer-Chip Assembly for Large-Scale Integration", IEEE Trans. Elec. Dev., Vol. ED-15, No. 9, September 1968.
For very high-density packaging, it is known in the prior art to use a combination of these two techniques (i.e., "flip-chip" and "chip-on-board") to provide multi-tier "flip-chip" assemblies. Examples of prior-art multi-tier flip-chip assemblies are found in U.K. patent application No. GB 2117564, filed on Mar. 26, 1982 by Talbot and Richer; Japanese Patent No. 60-94756, issued May 27, 1985 to Shiyuzou Akeshima; Japanese Patent No. 57-31166, issued Feb. 9, 1982 to Jiyunji Sakurai (hereinafter "SAKURAI"); and Japanese Patent No. 55-111151, issued Aug. 27, 1980 to Kenichi Oono.
The technique of "bump-bonding" is well known in the prior-art, and has a great many variations. Various examples of processes and techniques associated with bump bonding are given in U.S. Pat. No. 4,717,066, issued Jan. 5, 1988 to Goldenberg et al.; U.S. Pat. No. 5,066,614, issued Nov. 19, 1991 to Dunaway et al.; U.S. Pat. No. 5,074,947, issued Dec. 24, 1991 to Estes et al.; U.S. Pat. No. 4,700,276, issued Oct. 13, 1987 to Freyman et al.; and U.S. Pat. No. 4,817,850 issued Apr. 4, 1989 to Wiener-Avnear et al.. These patents represent a wide variety of techniques for providing bump connections. Hereinafter, the terms "bump bonding" and "bump contacts" will refer to these or any other suitable technique for providing raised electrical and mechanical connections between planar surfaces.
In a typical multi-tier flip-chip assembly of the prior art, a first integrated circuit die is attached (mounted) by its bottom surface to the top surface of a passive substrate. The top surface of the first die has a number of contact areas (e.g., bond pads or solder bumps). A first portion of the contact areas are wire bonded on a one-to-one basis to conductive traces on the top surface of the substrate. Another portion of the contact areas are arranged in a pattern to match a pattern of mating bump contacts disposed on a top (circuit side) surface of a second "flip chip" integrated circuit die, which is flipped over (inverted) onto the top surface of the first integrated circuit die such that the bottom side of the second "flip-chip" integrated circuit die is up and the pattern of its bump contacts aligns with pattern of the mating contact areas on the first integrated circuit die. The bump contacts are then "fused" or permanently connected to the contact areas (by heating of solder bumps, or polymerization or curing or conductive polymer bumps, or other suitable technique). This type of assembly is exemplary the prior-art concept of combining chip-on-board technology with flip-chip technology.
A technique for increasing circuit density using a flip-chip configuration is described in IBM Technical Disclosure Bulletin, Vol 28, No. 2, July, 1985, entitled "Mated Array Chip Configuration" (hereinafter "IBM-1") whereby identical semiconductor chips with common (interchangeable) input/output pads are mated together by what IBM describes as "conventional C4" (controlled collapse chip connection) chip-joining technology (a flip-chip joining method) in an offset configuration. More particularly, a first set of identical chips is mounted in a coplanar, closely spaced configuration, with gaps between the chips. A second set of chips, also identical to the each other and to the first set of chips is flip-chip mounted by bump contacts over the first set of chips, in a manner similar to that described hereinabove except that there is a very slight horizontal offset between the first and second sets of chips permitting each of the second set of chips to span one of the gaps between the first set of chips and make electrical connections with two of the first set of chips. Each of the second set of chips has a large (substantial) portion of its surface area over one of the first set of chips and a very small portion (just enough to make electrical connections with a few edge-positioned bump contacts) over another of the first set of chips. In this staggered configuration, it is possible to effectively double the density of a semiconductor assembly on a given area of substrate.
Inasmuch as the object of the IBM technique described in IBM-1 is to increase circuit density, a very large overlap is required between the faces of the first set of dies (chips) and the second set of dies. While this configuration doubles circuit density, it also doubles the amount of power being dissipated within the same area (e.g., the area of one chip), and can cause local heating or "hot spots" on the dies, if any appreciable amount of power is dissipated by the dies. In high-speed semiconductor devices, it is not uncommon for significant amounts of heat to be dissipated.
Further, since identical dies are used, this particular flip-chip configuration is limited to increasing the bit densities of arrays of memories or functional devices, and is not suited to stacking dissimilar chips having diverse functions.
One problem with chip-on-board assemblies is the amount of time and expense required to attach the bond wires to the dies. While this process is largely automated, bond wires must still be attached to the die one at a time. This process can become expensive where large numbers of dies are involved. The flip-chip technique overcomes this problem.
A typical prior art "silicon circuit board" using flip-chips has a passive substrate material with wiring patterns, a number of flip-chips disposed on one surface and connected via bump connections to selected ones of the conductive traces.
Double-sided assemblies are also known in the prior art. For example, a multi-layer ceramic (or similar) printed substrate has contact areas are disposed on both sides of the substrate. Integrated circuit dies are "flipped" onto both sides of the passive substrate. The same technique may be applied to chip-on-board technology to provide double-sided chip-on-board assemblies.
Depending upon the type of circuitry used, flip-chip assemblies may have power dissipation problems. If one chip is being assembled face-to-face with another, the power dissipated by the two chips in close proximity may cause local heating, leading to eventual device failure. Careful thermal design of flip-chip assemblies is necessary to overcome this problem. One approach in the prior art has been to encapsulate the assembly in a thermally conductive compound which is attached to a good heat sink, helping to eliminate the local heating problem
Multi-tier die packages have been employed in the prior-art to increase packaging density. In such packages a multi-tier ceramic package assembly having alternating patterned conductive traces and insulating ceramic layers arranged in a "sandwich" configuration is employed. A centrally located first opening in a first inner insulating layer exposes a portion of the underlying layers. A first set of patterned conductive traces along the top of the layer extend to the edges of the first opening. A second insulating layer, located above the first insulating layer has a larger centrally located second opening which exposes the first opening, a portion of the first insulating layer around the first opening, and a portion of the first set of patterned conductive traces around the periphery of the opening. A second set of patterned conductive traces extend along the top surface of the second insulating layer to the edges of the second opening therein. A third insulating layer, located above the first and second insulating layers, has a still larger centrally located third opening which exposes the first and second openings in the underlying layers and a portion of the second set of patterned conductive traces around the periphery of the second opening. Progressively larger openings in other insulating layers and additional sets of patterned conductive traces are added in this fashion, as required, to form a "stepped" opening into the package body.
Integrated circuit dies are then assembled into a pyramid-shaped stack with insulating spacers between the dies. The die stack is assembled into the stepped opening. As many dies are assembled as there are levels in the "stepped" opening in the ceramic package body. Bond pads are exposed around the periphery of each die. Bond wires connect the bond pads of each die to patterned conductive traces on corresponding "levels" of the stepped package body.
In prior-art multi-chip assemblies employing wire bonding, bond wires are attached with equipment that makes the connections one at a time. The process of making these connections can become both time consuming and expensive.
One prior-art technique, disclosed in "SAKURAI" eliminates the bond wires by making a flip-chip assembly out of a stack of dies, providing bump contacts around the edges of each die in the stack, then flipping the assembly onto a ceramic package assembly which has stepped openings sized such that the steps of the flip-chip assembly, formed by the edges of the dies, rest on the edges of the openings in the package assembly. Conductive traces on the ceramic package assembly align with the bump contacts, providing electrical connections thereto, as well as facilitating the mechanical mounting of the stacked die assembly.
While this type of assembly solves many problems, it presents alignment problems of its own. The relative heights of the die-insulator stack and the layers of the ceramic substrate assembly must be carefully controlled if all of the dies are to rest properly on the corresponding layer of the package. Shifts in relative positioning of the ceramic layers (i.e., sliding of one against the other during the assembly process) must be minimized, as must shifts in relative positioning of the dies in order to achieve proper alignment of bump contacts with conductive traces. Errors in placement of layers and/or dies are cumulative, so extreme precision is required of the assembly process.
The aforementioned stacked die assemblies do not provide for inter-die connections, other than by means of internal connections in the ceramic substrate assembly (package) or by means of external wiring. Since inter-die connections may be radically different from one application to another, it may be necessary to provide a different custom ceramic substrate assembly for each application, preventing the use of standard packaging. If standardized packaging is used, then it may be necessary to accomplish inter-die connections external to the package. This lengthens signal paths and necessitates extra pins on the package for signals which might otherwise remain internal to the package. When signals are brought out of the package, all of the aforementioned attendant signal drive issues re-surface, partially eliminating the benefit of the high-density packaging technique.
Various prior-art schemes are available to assist in positioning of flip-chip assemblies. Some examples are found in U.S. Pat. No. 3,811,186, issued on May 21, 1974 to Larnerd et al; U.S. Pat. No. 4,949,148, issued on Aug. 14, 1990 to Bartelink; and in Japanese Patent No. 60-49638, issued Mar. 18, 1985 to Kazuhito Ozawa. These techniques deal well with flip-chip assemblies, but alignment of chips bonded by their blank back side to a substrate is somewhat more difficult to achieve.
In summary, prior art techniques for stacking dies suffer from a number of problems, including local heat build-up, proliferation of bond wires, proliferation of pins (external package connections), and alignment difficulties. While one or more of these problems are addressed, in part, by some of the prior art techniques, no prior-art technique fully addresses all of these problems simultaneously. For example, while the multi-tier technique of SAKURAI eliminates the use of bond wires, it does not solve the local heat build-up problem or provide for inter-die connections.
Another problem remaining unaddressed by the prior art has to do with wiring density. As the number of interconnections increases in flip-chip applications, it can become difficult to find short routing paths around the connections to the die. Depending upon the substrate medium used, a limited number of wiring layers may be available, requiring long wiring paths or jumpers. Alternatively, for some substrate media, it may become necessary to use additional wiring layers, increasing the overall cost of the assembly.
Another insufficiency with the prior can be attributed to an emerging trend towards semiconductor devices with extremely large amounts of I/O (external connections). The periphery of a die (i.e., an area, or band, just inward the edges of the die) is used to provide external connections, typically by providing bond pads to which bond wires (e.g.) may be connected. Many modern integrated circuit designs are "pad limited." In other words, a die of a given area has a fixed, limited amount of periphery available for bond pads. On many modern integrated circuit designs, especially as transistor geometries are decreased, the peripheral (bonding) area of a die is simply not sufficient for the large number of bond pads desired, when the die is sized just large enough to hold the active circuitry of the design.
Commonly owned, co-pending U.S. patent application Ser. No. 916,328, filed Jul. 17, 1992 by Rostoker discloses a technique for providing greater amount of I/O (e.g., bond pads) by using "certain non-square" die shapes which increase the periphery to area ratio for the die, as compared with square and low-aspect-ratio rectangular dies. Hence, the "certain non-square" die shapes disclosed therein provide for a greater amount of I/O in a die of a given area. However, it may well be the case that "standard" packaging techniques, namely those designed to accommodate "standard" square and low-aspect-ration rectangular dies, will not adapt well to the "certain non-square" die shapes. For example, signal paths may become unacceptably long.